Limited switch dynamic logic circuits for high-speed low-power circuit design

Authors:
W. Belluomini;D. Jamsek;A. K. Martin;C. McDowell;R. K. Montoye;H. C. Ngo;J. Sawada
Affiliations:
-;-;-;-;-;-;-
Venue:
IBM Journal of Research and Development
Year:
2006

Citing 2
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Abstract

This paper describes a new circuit family--limited switch dynamic logic (LSDL). LSDL is a hybrid between a dynamic circuit and a static latch that combines the desirable properties of both circuit families. The paper also describes many enhancements and extensions to LSDL that increase its logical capability. Finally, it presents the results of two multiplier designs, one fabricated in 130- nm technology and one in 90-nm technology. The 130- and 90-nm designs respectively reach speeds up to 2.2 GHz and 8 GHz.