Clock-delayed domino for dynamic circuit design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
A pipelined clock-delayed domino carry-lookahead adder
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Computation of joint timing yield of sequential networks considering process variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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In recent years, wave-pipelined domino logic has received much attention as a means to implement high-speed circuits. However, this logic is vulnerable to parametric variations and the situation will degrade as technology scales down. In this paper, statistical timing relations are developed for characterizing performance impacts of parametric variations in different wave-pipelined domino circuits and clocking styles. Analytic results show that wave pipeline built with footless non-blocking domino cell accumulates timing variations due to parametric variation along the pipeline. Thus performance reduces with pipeline size as variations accumulate. On the other hand, wave pipelined footed blocking domino logic is less sensitive to parametric variations. Simulation results of a 6-stage wave pipeline using footed blocking domino cells in 130nm technology also demonstrate the advantages of this logic style both in performance and power consumption.