Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A pipelined clock-delayed domino carry-lookahead adder
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs
Microelectronics Journal
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
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Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is as easy to design with as static CMOS circuits from a logic design and synthesis perspective. Design tools developed for static CMOS are used as part of a methodology for automating the design of CD domino circuits. The methodology and CD domino's characteristics are demonstrated in the design of a 32-b carry look-ahead adder. The adder was fabricated with MOSIS's 0.8-/spl mu/m CMOS process with scalable CMOS design rules that allow a 1.0-/spl mu/m drawn gate length. Measurements of the adder show a worst case addition of 2.1 ns. The CD domino adder is 1.6/spl times/ faster than a dual-rail domino adder designed with the same cell library and technology.