ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Clock-delayed domino for dynamic circuit design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Elements of low power design for integrated systems
Proceedings of the 2003 international symposium on Low power electronics and design
On circuit techniques to improve noise immunity of CMOS dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital Circuit Optimization via Geometric Programming
Operations Research
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive keeper design for dynamic logic circuits using rate sensing technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, the VLSI Journal
Low power wide gates for modern power efficient processors
Integration, the VLSI Journal
| Hi-index | 0.00 |
A new high-speed Domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-Dominion logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends Domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascade voltage switch (DDCVS) logic.