Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Energy: efficient instruction dispatch buffer design for superscalar processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power efficient comparators for long arguments in superscalar processors
Proceedings of the 2003 international symposium on Low power electronics and design
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Proceedings of the conference on Design, automation and test in Europe
A high speed and leakage-tolerant domino logic for high fan-in gates
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Register file partitioning and compiler support for reducing embedded processor power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, the VLSI Journal
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In this paper, a low power register file and tag comparator is proposed which has lower leakage and higher noise immunity without dramatic speed degradation due to the wide fan-in gates. Simulation of register files and tag comparators designed is done using low-V"t"h 90nm CMOS process technology model in all process corners. The results demonstrate 20% power reduction and 2x noise-immunity improvement in the implemented register file using the proposed circuit at the same delay compared to the standard domino circuits. On the other hand, simulation of tag comparators implemented using the other proposed circuit shows 41%, 22% and 7.5% reduction in power, delay and area, respectively compared to the standard footless domino at the same robustness condition. Moreover, the register file and the tag comparator designed with the proposed circuits respectively show 2.48 and 3 times improvement in the defined figure of merit compared to the counterpart circuits designed with the conventional domino circuit. Thus, the proposed are power efficient and suitable approaches for embedded processors with multi-ported register file and fully-associative caches with large number of tag comparators.