Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, the VLSI Journal
Domino logic designs for high-performance and leakage-tolerant applications
Integration, the VLSI Journal
Low power wide gates for modern power efficient processors
Integration, the VLSI Journal
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Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in and high-speed applications in ultra deep submicron technologies. The proposed circuit employs a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. According to simulations in a predictive 70nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention between keeper transistor and NMOS evaluation transistors at the beginning of evaluation phase. This results in less power dissipation for the proposed technique.