Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies

Authors:
Bhaskar Chatterjee;Manoj Sachdev;Ram Krishnamurthy
Affiliations:
-;-;-
Venue:
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Year:
2004

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Abstract

In this paper, we discuss the design of leakage tolerant wide-OR domino gates for deep submicron (DSM), bulk CMOS technologies. Technology scaling is resulting in 3-5x increasein transistor IOFF/µm per generation resulting in 15%-30% noise margin degradation of high performance domino gates. We investigate several techniques that can improve the noise margin of domino logic gates and thereby ensure their reliable operation for sub-130nm technologies. Our simulations indicate that, selective usage of dual VTH transistors shows acceptable energy-delay tradeoffs for the 90nm technology. However, techniques like supply voltage (Vcc) reduction and using non-minimum Le transistors are required in order to ensure robust and scalable wide-OR domino designs for the 70nm generation.