High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Domino logic with variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel dual-Vth independent-gate FinFET circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32nm FinFET technology.