Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages

Authors:
Zhiyu Liu;Volkan Kursun
Affiliations:
University of Wisconsin - Madison;University of Wisconsin - Madison
Venue:
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Year:
2006

Citing 6
Cited 2

Low power design challenges for the decade (invited talk)

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low swing dual threshold voltage domino logic

Proceedings of the 12th ACM Great Lakes symposium on VLSI
Reduced dynamic swing domino logic

Proceedings of the 13th ACM Great Lakes symposium on VLSI
Issues in the Design of Domino Logic Circuits

GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Circuit Design Techniques for a Gigahertz Integer Microprocessor

ICCD '98 Proceedings of the International Conference on Computer Design
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits

ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design

FinFET domino logic with independent gate keepers

Microelectronics Journal
Switching and leakage power modeling for multiple-supply dynamic gate with delay constraining based on wavelet neural networks

IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at inputs and outputs for robust and high speed operation. Power supply, ground, and threshold voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 51.9% as compared to the standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 40.4% due to the lower switching power required to charge/discharge the dynamic node. Furthermore, the evaluation speed and noise immunity are enhanced by up to 19.4%and 39.1%, respectively, as compared to the standard fullswing circuits. The proposed low swing technique also reduces the idle mode leakage power consumption of high fan-in domino gates by up to 84.2%.