Energy-efficient dynamic circuit design in the presence of crosstalk noise
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Issues in the Design of Domino Logic Circuits
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Reduced dynamic swing domino logic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Managing static leakage energy in microprocessor functional units
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Sleep switch dual threshold voltage domino logic with reduced standby leakage current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Compiler-assisted leakage energy optimization for clustered VLIW architectures
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
A predictably low-leakage ASIC design style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiler-assisted instruction decoder energy optimization for clustered VLIW architectures
HiPC'07 Proceedings of the 14th international conference on High performance computing
Compiler-assisted power optimization for clustered VLIW architectures
Parallel Computing
Domino logic with variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiler-assisted energy optimization for clustered VLIW processors
Journal of Parallel and Distributed Computing
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal
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A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A simple and efficient dual threshold voltage (dual-Vt) circuit technique that incorporates low swing signals is also proposed. It is shown that the proposed dual-Vt technique reduces the standby leakage current by approximately 235 times while offering enhanced delay characteristics as compared to a standard low threshold voltage implementation.