Fundamentals of algorithmics
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low swing dual threshold voltage domino logic
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
A survey of design techniques for system-level dynamic power management
Readings in hardware/software co-design
A comprehensive high-level synthesis system for control-flow intensive behaviors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On multiple-voltage high-level synthesis using algorithmic transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
High performance low power CMOS dynamic logic for arithmetic circuits
Microelectronics Journal
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal
Low-Power Multiplier Design Using a Bypassing Technique
Journal of Signal Processing Systems
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for hardware allocation in data path synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect-aware low-power high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bitwise scheduling to balance the computational cost of behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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State of the art multi-objective synthesis flows use to degrade some parameters of the circuit while trying to optimize the target one. This paper addresses the power reduction problem in heterogeneous datapaths, while keeping a similar area and execution time with respect to the baseline case. Our specific approach first diminishes the area via fragmentation techniques and afterwards it gives it back with the introduction of Low Power Functional Units (LP-FUs) that occupy more area than their corresponding non-low power counterparts. Furthermore, a fragmentation algorithm more suitable for power reduction is proposed. Results show that it is possible to diminish power by 27% on average (49% in the best case).