A neural net based self organising scheduling algorithm
EURO-DAC '90 Proceedings of the conference on European design automation
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Novel algorithms for the simultaneous cost/resource-constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed. The entire allocation process can be formulated as a two-dimensional placement problem of microinstructions in space and time. This formulation readily lends itself to the use of a variety of heuristics for solving the allocation problem. The authors present simulated-annealing-based algorithms which provide excellent solutions to this formulation of the allocation problem. These algorithms operate under a variety of user-specifiable constraints on hardware resources and costs. They also incorporate conditional resource sharing and simultaneously address all aspects of the allocation problem, namely register, arithmetic unit, and interconnect allocation, while effectively exploring the existing tradeoffs in the design space