Estimating architectural resources and performance for high-level synthesis applications
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Cathedral-II: A Silicon Compiler for Digital Signal Processing
IEEE Design & Test
An Introduction to High-Level Synthesis
IEEE Design & Test
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithms for hardware allocation in data path synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A prescriptive formal model for data-path hardware
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper focuses on the resource sharing problem when performing high-level synthesis. It argues that the conventionally accepted synthesis flow when resource sharing is done after scheduling is sub-optimal because it cannot account for timing penalties from resource merging. The paper describes a competitive approach when resource sharing and scheduling are performed simultaneously. It provides a quantitative evaluation of both approaches and shows that performing sharing during scheduling wins over the conventional approach in terms of quality of results.