Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications
Computers and Electrical Engineering
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
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The article describes the status of work at IMEC on the Cathedral-II silicon compiler. The compiler was developed to synthesizesynchronous multiprocessor system chips for digital signal processing. It is a continuation of work on the Cathedral-I operationalsilicon compiler for bit-serial digital filters. Cathedral-II is based on a ?meet in the middle? design method that encouragesa total separation between system design and reusable silicon design. The CAD system includes a rule-based synthesis program,a procedural program, and a controller synthesis environment. Processors are synthesized in terms of modules called from automatedreusable module generators. Chip layout is done on a floor planner. An expert subsystem verifies correctness during silicondesign and generates functional and timing models for verification at the module and chip levels.