Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Introduction to algorithms
Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding
IEEE Transactions on Computers
Determining the minimum iteration period of an algorithm
Journal of VLSI Signal Processing Systems
Cathedral-II: A Silicon Compiler for Digital Signal Processing
IEEE Design & Test
Optimal automatic periodic multiprocessor scheduler for fullyspecified flow graphs
IEEE Transactions on Signal Processing
Architectural synthesis for DSP silicon compilers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Allocation of multiport memories in data path synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal approach to the scheduling problem in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Integrated Automated Layout Generation System for DSP Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated Synthesis of Data Paths in Digital Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A technique for scheduling and processor allocation leading to the synthesis of integrated heterogeneous pipelined processing elements, implementing digital signal processing applications, is proposed. The proposed technique achieves efficient hardware implementations at the logic-level by minimizing the number of processing units used, without compromising the rate and delay optimality criteria. The proposed algorithm is found to outperform algorithms resulting in homogeneous implementations, as it gives schedules with lower iteration periods, requires less hardware resources, and has lower time complexity at design time. In comparison with the already existing heterogeneous algorithms, the proposed algorithm produces schedules of lower time complexity and lower iteration period for some applications. The optimal performance of the proposed algorithm has been verified on several benchmarks.