High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications
Computers and Electrical Engineering
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This paper describes a method for formally modeling digital logic using algebraic relations. The relations model digital logic at the register-transfer (RT) level. An RT-level behaviorial specification is used to develop the relations, which express timing relationships that must be satisfied by any correct implementation. An extension of the model is shown which can be used for synthesis at the RT level. The growth rate and computational properties of the model are discussed, and an example of synthesis is shown.