High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications
Computers and Electrical Engineering
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
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A design methodology for automated mapping of DSP algorithms into VLSI architectures is presented. The methodology takes into account explicit algorithm requirements on throughput and latency, in addition to VLSI technology constraints on silicon area and power dissipation. Algorithm structure, design style of functional units, and parallellism of the architecture are all explored in the design space. The synthesized architecture is a multibus multifunction unit processor matched to the implemented algorithm. The architecture has a linear topology and uses a lower number of interconnects and multiplexer inputs compared to other synthesized architectures with random topology having the same performance. The synthesized processor is a self-timed element externally, while it is internally synchronous. The methodology is implemented in a design aid tool called SPAID. Results obtained using SPAID for two DSP algorithms compare favorably with other synthesis techniques