Memory Synthesis for FPGA-Based Reconfigurable Computers
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications
Computers and Electrical Engineering
| Hi-index | 0.03 |
An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example