Definition and solution of the memory packing problem for field-programmable systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Efficient resource arbitration in reconfigurable computing environments
DATE '00 Proceedings of the conference on Design, automation and test in Europe
High-level library mapping for memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers
Proceedings of the conference on Design, automation and test in Europe
Tabu Search
Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Architectures and algorithms for field-programmable gate arrays with embedded memory
Architectures and algorithms for field-programmable gate arrays with embedded memory
Allocation of multiport memories in data path synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
For data intensive applications like Digital Signal Processing, Image Processing, and Pattern Recognition, memory reads and writes constitute a large portion of the total design execution time. With the advent of on-chip memories, a rich hierarchy of physical memories is now available on a Reconfigurable Computer (RC). An intelligent usage of these memories can lead to a significant improvement in the latency of the overall design. This paper presents an automated heuristic-based memory mapping framework for RCs. We use a Tabu search guided heuristic, Rectangle Carving, to map a single data structure onto several instances of a memory type on the RC. We also introduce control logic to resolve potential memory access conflicts and to make the details of memory mapping transparent to the accessing logic.