Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers

  • Authors:
  • I. Ouaiss;R. Vemuri

  • Affiliations:
  • Digital Design Environments Lab, University of Cincinnati, Cincinnati, OH;Digital Design Environments Lab, University of Cincinnati, Cincinnati, OH

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2001

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Abstract