Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers
Proceedings of the conference on Design, automation and test in Europe
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Routing on field-programmable switch matrices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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