Switch module design with application to two-dimensional segmentation design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
FPGA routing and routability estimation via Boolean satisfiability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of FPGA/FPIC switch modules
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Routing for symmetric FPGAs and FPICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we address the problem of routing nets on field programmable gate arrays (FPGAs) interconnected by a switch matrix. We extend the switch matrix architecture proposed by Zhu et al. to route nets between FPGA chips in a multi-FPGA system. Given a limited number of routing resources in the form of programmable connection points within a two-dimensional switch matrix, this problem examines the issue of how to route a given net traffic through the switch matrix structure. First, we define the problem as a general undirected graph in which each vertex has one single color among six possible colors and formulate it as a constraint satisfaction problem. This is further modeled as a 0-1 multidimensional knapsack problem for which a fast approximate solution is applied. Experimental results show that the accuracy of our proposed heuristic is quite high for moderately large switch matrices.