Multiple-Way Network Partitioning
IEEE Transactions on Computers
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
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This paper presents a technique to perform partitioning and synthesis of behavioral specifications. Partitioning of the design is done under multiple constraints - interconnections and device areas of the reconfigurable architecture, and the latency of the design. The proposed Multi-FPGA partitioning technique (FMPAR) is based on the Fiduccia-Mattheyses (FM) partitioning algorithm. In order to contemplate multiple implementations of the behavioral design, the partitioner is tightly integrated with an area estimator and design space exploration engine.A partitioning and synthesis framework was developed, with the FMPAR behavioral partitioner at the front-end and various synthesis phases (High-Level, Logic and Layout) at the back end. Results are provided to demonstrate the advantage of tightly integrating exploration with partitioning. It is also shown that, in relatively short runtimes, FMPAR generates designs of similar quality compared to a Simulated Annealing partitioner. Designs have been successfully implemented on a commercial multi-FPGA board, proving the effectiveness of the partitioner and the entire design framework.