Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Technology mapping for FPGAs with embedded memory blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers
Proceedings of the conference on Design, automation and test in Europe
Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
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It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown that they can also be used to implement logic very efficiently. This previous work has only considered single-port arrays. Many current FPGAs, however, contain dual-port arrays. In this paper we present an algorithm that maps logic to these dual-port arrays. Our algorithm can either optimize area with no regard for circuit speed, or optimize area under the constraint that the combinational depth of the circuit does not increase. Experimental results show that, on average, our algorithm packs between 29% and 35% more logic than an algorithm that targets single-port arrays. We also show, however, that even with this algorithm, dual-port arrays are still not as area-efficient as single-port arrays when implementing logic.