An output encoding problem and a solution technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Technology mapping for FPGAs with embedded memory blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
FSM Decomposition for Low Power in FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compiling PCRE to FPGA for accelerating SNORT IDS
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Computers and Electrical Engineering
Journal of Computer and Systems Sciences International
Sequential algorithm for low-power encoding internal states of finite state machines
Journal of Computer and Systems Sciences International
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Modern FPGAs contain on-chip synchronous embedded memory blocks (SEMBs), these memory blocks can be used to implement control units, when not used as on-chip memory. In this paper, we explore the mapping of Finite State Machines (FSMs) into the SEMBs for power and area minimization. We have shown the SEMB based implementation of the FSMs and compared it with conventional Flip-Flop (FF) based implementation. The proposed implementation of the FSMs consumes less power and has lower area and routing overhead than the FF based approach and it can be clocked at the maximum clock frequency supported by the SEMBs. Experimental results show that the SEMB based FSM consumes 4% to 26% less power than the conventional implementation. In addition it is observed that the power consumption can be further reduced by stopping the clock to the SEMBs during the idle states.