An output encoding problem and a solution technique

Authors:
Subhasish Mitra;LaNae J. Avra;Edward J. McCluskey
Affiliations:
Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, California;Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, California;Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, California
Venue:
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Year:
1997

Citing 7
Cited 4

Logic design principles with emphasis on testable semicustom circuits

Logic design principles with emphasis on testable semicustom circuits
Introduction to algorithms

Introduction to algorithms
Sequential Logic Synthesis

Sequential Logic Synthesis
Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis
Scan Synthesis for One-Hot Signals

Proceedings of the IEEE International Test Conference
An Output Encoding Problem and A Solution Technique

An Output Encoding Problem and A Solution Technique
Synthesis of multi-level logic with one symbolic input

EURO-DAC '91 Proceedings of the conference on European design automation

SCAN SYNTHESIS FOR ONE-HOT SIGNALS

ITC '97 Proceedings of the 1997 IEEE International Test Conference
Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Novel state minimization and state assignment in finite state machine design for low-power portable devices

Integration, the VLSI Journal
Novel state minimization and state assignment in finite state machine design for low-power portable devices

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a new output encoding problem as follows: Given a specification table, such as a truth table or a finite state machine state table, where some of the outputs are specified in terms of 1's, 0's and don't cares, and others are specified symbolically, and assuming that the minimum number of bits are used to encode the symbolic outputs (ceiling(log_2_(n)) bits for n symbolic outputs), determine a binary code for each symbol of the symbolically specified output column such that the total number of output functions to be implemented after encoding the symbolic outputs and compacting the columns is minimum. There are several applications of this output encoding problem, one of which is to reduce the area overhead while implementing scan or pseudo-random BIST in a circuit with one-hot signals. We develop an exact algorithm to solve the above problem and present experimental data to validate the claim that our encoding strategy helps to reduce the area of a synthesized circuit.