Invited talk: algorithms for multi-level logic synthesis
Proceedings of the fifth MIT conference on Advanced research in VLSI
A kernel-finding state assignment algorithm for multi-level logic
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
ALU synthesis from HDL descriptions to optimized multi-level logic
EURO-DAC '92 Proceedings of the conference on European design automation
Representing the hardware design process by a common data schema
EURO-DAC '92 Proceedings of the conference on European design automation
An output encoding problem and a solution technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
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This paper presents algorithms that perform multi-level logic synthesis on logic with one symbolic input. This method contrasts to existing approaches that encode a symbolic input before logic synthesis. These approaches determine the encoding based on heuristic estimates. Our algorithms, which perform logic synthesis directly on the logic with the symbolic input, enable us to encode the symbolic input after logic synthesis. Since we determine the encoding based on the result of the multi-level logic synthesis, instead of heuristic estimates, we obtain better encoding and hence smaller logic. Experiments on a number of benchmarks show improvements up to 49%.