FSM decomposition revisited: Algebraic structure theory applied to MCNC benchmark FSMs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Low power state assignment targeting two-and multi-level logic implementations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Transformation and synthesis of FSMs for low-power gated-clock implementation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low power realization of finite state machines—a decomposition approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Spanning tree based state encoding for low power dissipation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Decomposition of Finite State Machines for Area, Delay Minimization
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Exact and heuristic algorithms for the minimization of incompletely specified state machines
EURO-DAC '91 Proceedings of the conference on European design automation
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Modeling Decentralized Real-Time Control by State Space Partition of Timed Automata
DS-RT '05 Proceedings of the 9th IEEE International Symposium on Distributed Simulation and Real-Time Applications
Reducing and smoothing power consumption of ROM-based controller implementations
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Low power finite state machine synthesis using power-gating
Integration, the VLSI Journal
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In this paper, the realization of low power finite state machines (FSMs) on FPGAs using decomposition techniques is addressed. The original FSM is divided into two submachines using a probabilistic criterion. Only one submachine is active at a time, meanwhile the other is disabled to save power. Different deactivation alternatives and state encoding have been studied. For each option, actual measurements of power consumption have been done using the MCNC and the PREP benchmark circuits. A Xilinx XC4K device has been utilized as technological framework. The proposed technique fits well with big FSM, where power reductions up to 46% are obtained.