Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Re-encoding sequential circuits to reduce power dissipation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Precomputation-based sequential logic optimization for low power
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Transformation and synthesis of FSMs for low-power gated-clock implementation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A new approach to effective circuit clustering
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A bipartition-codec architecture to reduce power in pipelined circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Synthesis of low-power selectively-clocked systems from high-level specification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance analysis of a transaction based software system with shutdown
Proceedings of the 2nd international workshop on Software and performance
FSM decomposition by direct circuit manipulation applied to low power design
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
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Mobile Networks and Applications
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FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
ILP-based optimization of sequential circuits for low power
Proceedings of the 2003 international symposium on Low power electronics and design
Discrete Applied Mathematics - Submodularity
Decomposition of Extended Finite State Machine for Low Power Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Decomposition of Extended Finite State Machine for Low Power Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Decomposition of instruction decoders for low-power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory
Integration, the VLSI Journal
Modeling the energy cost of applications on portable wireless devices
Proceedings of the 11th international symposium on Modeling, analysis and simulation of wireless and mobile systems
Genetic algorithm-based FSM synthesis with area-power trade-offs
Integration, the VLSI Journal
A three-step decomposition method for the evolutionary design of sequential logic circuits
Genetic Programming and Evolvable Machines
Power optimization using dynamic power management
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Low power finite state machine synthesis using power-gating
Integration, the VLSI Journal
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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We present in this article a new approach to the synthesis problem for finite state machines with the reduction of power dissipation as a design objective. A finite state machine is decomposed into a number of coupled submachines. Most of the time, only one of the submachines will be activated which, consequently, could lead to substantial savings in power consumption. The key steps in our approach are: (1) decomposition of a finite state machine into submachines so that there is a high probability that state transitions will be confined to the smaller of the submachines most of the time, and (2) synthesis of the coupled submachines to optimize the logic circuits. Experimental results confirmed that our approach produced very good results (in particular, for finite state machines with a large number of states.)