Low power state assignment targeting two-and multi-level logic implementations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Transformation and synthesis of FSMs for low-power gated-clock implementation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low power realization of finite state machines—a decomposition approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
State assignment for FSM low power design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Spanning tree based state encoding for low power dissipation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Low power sequential circuit design by using priority encoding and clock gating
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
FSM decomposition by direct circuit manipulation applied to low power design
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
State Assignment for Power and Area Minimization
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Low power FSM design using Huffman-style encoding
EDTC '97 Proceedings of the 1997 European conference on Design and Test
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
ILP-based optimization of sequential circuits for low power
Proceedings of the 2003 international symposium on Low power electronics and design
A new state assignment technique for testing and low power
Proceedings of the 41st annual Design Automation Conference
Low power synthesis of finite state machines with mixed D and T flip-flops
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
FSM re-engineering and its application in low power state encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal and Power Management of Integrated Circuits (Series on Integrated Circuits and Systems)
Thermal and Power Management of Integrated Circuits (Series on Integrated Circuits and Systems)
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NOVA: state assignment of finite state machines for optimal two-level logic implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low power finite state machine synthesis using power-gating
Integration, the VLSI Journal
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Traditionally, state-encoding strategies targeting minimization of area, dynamic power or a combination of them have been utilized in finite state machine (FSM) synthesis. With drastic scaling down of devices at recent technology level, leakage power has also become an important design parameter to be considered during synthesis. A genetic algorithm-based state encoding, targeting area and power minimized FSM, has been proposed in this paper. A unified technique to reduce both static power (leakage) and dynamic power along with area trade-off has been carried out for FSM synthesis, targeting static CMOS NAND-NAND PLA, dynamic CMOS NOR-NOR PLA and pseudo-NMOS NOR-NOR PLA implementations. Suitable weights for area, leakage power and dynamic power to minimize power density have also been explored. Simulation with MCNC benchmarks shows an average improvement of 31%, 26% and 29% in leakage power consumption, dynamic power consumption and area requirement respectively, over NOVA-based state assignment technique in case of dynamic CMOS PLA implementation. Improvements of 30% in leakage power and 15% in area have been obtained for pseudo-NMOS PLA implementation. For the static CMOS case, the improvements are about 29% in leakage power consumption, 14% in dynamic power consumption and 18% in area requirement.