Merging multiple FSM controllers for DFT/BIST hardware
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Genetic algorithm-based FSM synthesis with area-power trade-offs
Integration, the VLSI Journal
Integration, the VLSI Journal
Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM
International Journal of Applied Mathematics and Computer Science
Low power finite state machine synthesis using power-gating
Integration, the VLSI Journal
Area and speed oriented synthesis of FSMs for PAL-based CPLDs
Microprocessors & Microsystems
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Encoding multi-valued functions for symmetry
Proceedings of the International Conference on Computer-Aided Design
Sequential algorithm for low-power encoding internal states of finite state machines
Journal of Computer and Systems Sciences International
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The problem of encoding the states of a synchronous finite state machine (FSM) so that the area of a two-level implementation of the combinational logic is minimized is addressed. As in previous approaches, the problem is reduced to the solution of the combinatorial optimization problems defined by the translation of the cover obtained by a multiple-valued logic minimization or by a symbolic minimization into a compatible Boolean representation. The authors present algorithms for this solution, based on a novel theoretical framework that offers advantages over previous approaches to develop effective heuristics. The algorithms are part of NOVA, a program for optimal encoding of control logic. Final areas averaging 20% less than other state assignment programs and 30% less than the best random solution have been obtained. Literal counts averaging 30% less than the best random solutions have been obtained