Synthesis of finite state machines: logic optimization
Synthesis of finite state machines: logic optimization
Synthesis of Finite State Machines: Functional Optimization
Synthesis of Finite State Machines: Functional Optimization
Logic Synthesis for Control Automata
Logic Synthesis for Control Automata
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
The Design Warrior's Guide to FPGAs
The Design Warrior's Guide to FPGAs
NOVA: state assignment of finite state machines for optimal two-level logic implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of finite state machines for CPLDs
International Journal of Applied Mathematics and Computer Science - Special Section: Robot Control Theory Cezary Zielinski
Design of microprogrammed controllers to be implemented in FPGAs
International Journal of Applied Mathematics and Computer Science - SPECIAL SECTION: Efficient Resource Management for Grid-Enabled Applications
Area and speed oriented synthesis of FSMs for PAL-based CPLDs
Microprocessors & Microsystems
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Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.