Synthesis of finite state machines: logic optimization
Synthesis of finite state machines: logic optimization
Logic Synthesis for Control Automata
Logic Synthesis for Control Automata
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Evolutionary Algorithm for State Assignment of Finite State Machines
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
State Assignment for PAL-based CPLDs
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM
International Journal of Applied Mathematics and Computer Science
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The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.