Area and speed oriented synthesis of FSMs for PAL-based CPLDs

Authors:
R. Czerwinski;D. Kania
Affiliations:
Silesian University of Technology, Institute of Electronics, Akademicka Str. 16, 44-100 Gliwice, Poland;Silesian University of Technology, Institute of Electronics, Akademicka Str. 16, 44-100 Gliwice, Poland
Venue:
Microprocessors & Microsystems
Year:
2012

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Abstract

New two-step methods of FSMs synthesis for PAL-based CPLDs are presented in the paper. The methods strive to find the optimum fit for a FSM to the structure of CPLD and aim at area and speed optimization. The first step for both methods is original state assignment that includes: techniques of two-level minimization, the limited number of terms contained in the cell and elements of adjusting to the logic optimization. The second step in the method oriented toward area minimization is PAL-oriented multi-level optimization, which is a search for implicants that can be shared by several functions. The second step in the method oriented toward speed maximization is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block.