Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Timed shared circuits: a power-efficient design style and synthesis tool
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis of finite state machines: logic optimization
Synthesis of finite state machines: logic optimization
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ACTion: combining logic synthesis and technology mapping for MUX-based FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
On-the-fly layout generation for PTL macrocells
Proceedings of the conference on Design, automation and test in Europe
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Transforming boolean relations by symbolic encoding
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Linear Transformations and Exact Minimization of BDDs
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
An Exact Input Encoding Algorithm for BDDs Representing FSMs
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
FSM re-engineering and its application in low power state encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Global rebuilding of OBDD's avoiding memory requirement maxima
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Linear sifting of decision diagrams and its application in synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of fully testable circuits from BDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area and speed oriented synthesis of FSMs for PAL-based CPLDs
Microprocessors & Microsystems
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We address the problem of encoding the state variables of a finite state machine such that the BDD representing the next state function and the output function has the minimum number of nodes. We present an exact algorithm to solve this problem when only the present state variables are encoded. We provide results on MCNC benchmark circuits.