Low power state assignment targeting two-and multi-level logic implementations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Re-encoding for low power state assignment of FSMs
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Spanning tree based state encoding for low power dissipation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Genetic algorithm-based FSM synthesis with area-power trade-offs
Integration, the VLSI Journal
FSM Encoding for BDD Representations
International Journal of Applied Mathematics and Computer Science
Applying Weighted Finite State Machines to Protocol Performance Analysis
SEEFM '09 Proceedings of the 2009 Fourth South-East European Workshop on Formal Methods
Reducing and smoothing power consumption of ROM-based controller implementations
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
Energy efficient computation: A silicon perspective
Integration, the VLSI Journal
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We propose Finite State Machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization procedure. We start with any traditional FSM synthesis and optimization procedure; then re-construct a functionally equivalent but topologically different FSM based on the optimization objective; and conclude with another round of FSM synthesis and optimization (can be the same procedure) on the newly constructed FSM. This allows us to explore a larger solution space that includes synthesis solutions to the functionally equivalent FSMs instead of only the original FSM, making it possible to obtain solutions better than the optimal ones for the original FSM. Guided by the result of the first round FSM synthesis, the solution space exploration process can be rapid and cost-efficient.To demonstrate this framework, we develop a genetic algorithm and a fast heuristic to re-engineer a low power state encoding procedure POW3 [1]. On average, POW3 can reduce the switching activity by 12% over non-power-driven state encoding schemes on the MCNC FSM benchmarks. We then re-engineer these benchmarks by the proposed genetic algorithm and heuristic respectively. When we apply POW3 to the re-engineered FSMs, we observe an additional 8.9% and 6.0% switching activity reduction. This translates to an average of 7.9% energy reduction with little area increase. Finally, we obtain the optimal low power coding for benchmarks of small size from an integer linear programming formulation. We find that the POW3-encoded original FSMs are 27.0% worse than the optimal, but this number drops to 6.7% when we apply POW3 to the re-engineered FSMs.