Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
FSM Decomposition for Low Power in FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Low power FSM design using Huffman-style encoding
EDTC '97 Proceedings of the 1997 European conference on Design and Test
ITCC '02 Proceedings of the International Conference on Information Technology: Coding and Computing
Synchronization Processor Synthesis for Latency Insensitive Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An application of functional decomposition in ROM-based FSM implementation in FPGA devices
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
High-level synthesis: an essential ingredient for designing complex ASICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FSM re-engineering and its application in low power state encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
Journal of Signal Processing Systems
An output encoding problem and a solution technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault secure datapath synthesis using hybrid time and hardware redundancy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Interest in automated methodologies increased last decades due to the ever-growing processing complexity and time-to-market constraints. CAD tools prove their efficiency in power consumption management, which is nowadays a major constraint for embedded systems. Efficient low power techniques for Finite State Machine (FSM) design have been proposed for logic-based controllers. In this paper, we explore the circuit power consumption reduction when the FSM is mapped in ROM blocks. The described methodology achieves power reduction of ROM-based controllers through the transformation of don't care values in the decoder part of the design. This methodology allows a reduction of the number of resource commutations and smoothes them over the processing execution, limiting current spikes. Experiments show that the number of commutation can be decreased from 64% compared to an area-optimized ROM implementation.