Parallel program design: a foundation
Parallel program design: a foundation
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Synthesis of operation-centric hardware descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Action Systems in Pipelined Processor Design
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Decentralization of process nets with centralized control
PODC '83 Proceedings of the second annual ACM symposium on Principles of distributed computing
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
Hardware synthesis from guarded atomic actions with performance specifications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design with race-free hardware semantics
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Verifying Compiler Based Refinement of BluespecTM Specifications Using the SPIN Model Checker
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Classes and inheritance in actor-oriented design
ACM Transactions on Embedded Computing Systems (TECS)
Holistic verification: myth or magic bullet?
Proceedings of the 46th Annual Design Automation Conference
Reducing and smoothing power consumption of ROM-based controller implementations
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
ACM SIGDA Newsletter
ACM SIGDA Newsletter
Towards a synthesis semantics for systemC channels
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog incurs a performance penalty. The case study here shows that this need not be the case. If the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-written Verilog RTL. Differences in the hardware quality are dominated by architecture differences and, therefore, it is more important to explore multiple hardware architectures. This exploration is not practical without quality synthesis from higher-level languages.