ACM Transactions on Programming Languages and Systems (TOPLAS)
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
High-level synthesis: an essential ingredient for designing complex ASICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Model Checking Bluespec Specified Hardware Designs
MTV '07 Proceedings of the 2007 Eighth International Workshop on Microprocessor Test and Verification
On the Difficulties of Concurrent-System Design, Illustrated with a 2×2 Switch Case Study
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Suitability of mCRL2 for concurrent-system design: a 2 × 2 switch case study
FMCO'09 Proceedings of the 8th international conference on Formal methods for components and objects
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
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The underlying model of computation for PROMELA is based on interacting processes with asynchronous communication, and hence SPIN has been mainly used as a verification engine for concurrent software systems. On the other hand, hardware verification has mostly focused on clock synchronous register-transfer level (RTL) models. As a result, verification tools such as SMV which are based on synchronous state machine models have been used more frequently for hardware verification. However, as levels of abstractions are being raised in hardware design and as high-level synthesis is being promoted for synthesizing RTL, hardware design verification problems are changing in nature. In this paper, we consider a specific high-level hardware description langauge, namely, Bluespec System Verilog (BSV). The programming model of BSV is based on concurrent guarded actions, which we also call as Concurrent Action Oriented Specification (CAOS). High-level synthesis from BSV models has been shown to produce efficient RTL designs. Given the industry traction of BSV-based high-level synthesis and associated design flow, we consider the following formal verification problems: (i) Given a BSV specification ${\cal S}$ of a hardware design, does it satisfy certain temporal properties? (ii) Given a BSV specification ${\cal S}$, and an implementation Rsynthesized from ${\cal S}$ using a BSV-based synthesis tool, does Rconform to the behaviors specified by ${\cal S}$; that is, is Ra refinement of ${\cal S}$? (iii) Given a different implementation R茂戮驴synthesized from ${\cal S}$ using some other BSV-based synthesis tool, is R茂戮驴a refinement of Ras well? In this paper, we show how SPIN Model Checker can be used to solve these three problems related to the verification of BSV-based designs. Using a sample design, we illustrate how our approach can be used for verifying whether the designer intent in the BSV specification is accurately matched by its synthesized hardware implementation.