Notions of computation and monads
Information and Computation
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
ACM Transactions on Programming Languages and Systems (TOPLAS)
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
System Design with SystemC
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Formal Semantics for VHDL
Experience with Embedding Hardware Description Languages in HOL
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
A Monad for Basic Java Semantics
AMAST '00 Proceedings of the 8th International Conference on Algebraic Methodology and Software Technology
From Refutation to Verification
FORTE/PSTV 2000 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XIII) and Protocol Specification, Testing and Verification (PSTV XX)
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Verifying BDD Algorithms through Monadic Interpretation
VMCAI '02 Revised Papers from the Third International Workshop on Verification, Model Checking, and Abstract Interpretation
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
Proofs of Correctness of Cache-Coherence Protocols
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
InVeST: A Tool for the Verification of Invariants
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Abstract and Model Check While You Prove
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
PVS: Combining Specification, Proof Checking, and Model Checking
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
The Semantic Challenge of Verilog HDL
LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Verification of non-functional programs using interpretations in type theory
Journal of Functional Programming
A reflective functional language for hardware design and theorem proving
Journal of Functional Programming
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture
Proceedings of the 2008 ACM symposium on Applied computing
Leveraging sequential equivalence checking to enable system-level to RTL flows
Proceedings of the 45th annual Design Automation Conference
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
Verifying Compiler Based Refinement of BluespecTM Specifications Using the SPIN Model Checker
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Imperative Functional Programming with Isabelle/HOL
TPHOLs '08 Proceedings of the 21st International Conference on Theorem Proving in Higher Order Logics
Pragmatic equivalence and safety checking in Cryptol
Proceedings of the 3rd workshop on Programming languages meets program verification
Centaur Technology Media Unit Verification
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Automatic Formal Synthesis of Hardware from Higher Order Logic
Electronic Notes in Theoretical Computer Science (ENTCS)
Verification of AMBA Using a Combination of Model Checking and Theorem Proving
Electronic Notes in Theoretical Computer Science (ENTCS)
A monad-based modeling and verification toolbox with application to security protocols
TPHOLs'07 Proceedings of the 20th international conference on Theorem proving in higher order logics
Axiomatic constructor classes in Isabelle/HOLCF
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
Formalization of the DE2 language
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A trustworthy monadic formalization of the ARMv7 instruction set architecture
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
An industrially effective environment for formal hardware verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal verification of hardware synthesis
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We embed a non-trivial subset of Bluespec SystemVerilog (BSV) in the higher order logic of the PVS theorem prover. Owing to the clean semantics of BSV, application of monadic techniques leads to a surprisingly elegant embedding, in which hardware designs are translated into logic almost verbatim, preserving types and language constructs. The resulting specifications are compatible with the built-in model checker of PVS, which can automatically prove an important class of temporal logic theorems, and can also be used in conjunction with the powerful proof strategies of PVS, including automatic predicate abstraction, to verify a broader class of properties than can be achieved with model checking alone. Bluespec SystemVerilog is a hardware description language based on the guarded action model of concurrency. It has an elegant semantics, which has previously been shown to support design verification by hand proof: to date, however, little work has been conducted on the application of automated reasoning to BSV designs.