A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Floating Point Verification in HOL Light: The Exponential Function
Formal Methods in System Design
Proof planning for strategy development
Annals of Mathematics and Artificial Intelligence
Verifying the FM9801 Microarchitecture
IEEE Micro
Hardware/Software Partitioning in Verilog
ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
From Operational Semantics to Denotational Semantics for Verilog
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
IFM '00 Proceedings of the Second International Conference on Integrated Formal Methods
ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Formal verification of the FPGA cores
Nordic Journal of Computing
Highlevel verification of control intensive systems using predicate abstraction
Formal methods and models for system design
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
ICTAC'04 Proceedings of the First international conference on Theoretical Aspects of Computing
An automatic mapping from statecharts to verilog
ICTAC'04 Proceedings of the First international conference on Theoretical Aspects of Computing
Synchronous digital circuits as functional programs
ACM Computing Surveys (CSUR)
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The Verilog hardware description language (HDL) is widely used to model the structure and behavior of digital systems ranging from simple hardware building blocks to complete systems. Its semantics is based on the scheduling of events and the propagation of changes. Different Verilog models of the same device are used during the design process and it is important that these be `equivalent'; formal methods for ensuring this could be commercially significant. Unfortunately, there is very little theory available to help. This self-contained tutorial paper explains the semantics of Verilog informally and poses a number of logical and semantic problems that are intended to provoke further research. Any theory developed to support Verilog is likely to be useful for the analysis of the similar (but more complex) language VHDL.