From Operational Semantics to Denotational Semantics for Verilog
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
ProCoS Proceedings of the Third International Symposium Organized Jointly with the Working Group Provably Correct Systems on Formal Techniques in Real-Time and Fault-Tolerant Systems
A Normal Form Reduction Strategy for Hardware/Software Partitioning
FME '97 Proceedings of the 4th International Symposium of Formal Methods Europe on Industrial Applications and Strengthened Foundations of Formal Methods
The Semantic Challenge of Verilog HDL
LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science
Deriving Operational Semantics from Denotational Semantics for Verilog
APSEC '01 Proceedings of the Eighth Asia-Pacific on Software Engineering Conference
Partitioning Program into Hardware and Software
APSEC '01 Proceedings of the Eighth Asia-Pacific on Software Engineering Conference
An automatic mapping from statecharts to verilog
ICTAC'04 Proceedings of the First international conference on Theoretical Aspects of Computing
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We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The cospecification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Verilog. Facilitated by Verilog's rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.