An automatic mapping from statecharts to verilog

Authors:
Viet-Anh Vu Tran;Shengchao Qin;Wei Ngan Chin
Affiliations:
Vietsoftware Company, Hanoi, Vietnam;Singapore-MIT Alliance;Singapore-MIT Alliance
Venue:
ICTAC'04 Proceedings of the First international conference on Theoretical Aspects of Computing
Year:
2004

Citing 15
Cited 0

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Implementing Statecharts in PROMELA/SPIN

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ICFEM '00 Proceedings of the 3rd IEEE International Conference on Formal Engineering Methods
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Abstract

Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for both behavioural and structural specification of (hardware) systems. This paper implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.