An Approach to the Specification and Verification of a Hardware Compilation Scheme
The Journal of Supercomputing
From Operational Semantics to Denotational Semantics for Verilog
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
IFM '00 Proceedings of the Second International Conference on Integrated Formal Methods
ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
An automatic mapping from statecharts to verilog
ICTAC'04 Proceedings of the First international conference on Theoretical Aspects of Computing
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An operational semantics of a significant subset of the Verilog Hardware Description Language (HDL) is presented. The semantics is encoded using the logic programming language Prolog in a literate programming style. This allows the associated documentation to be maintained in step with the semantics, and the printed version to be presented in a standard mathematical operational semantics style. It also enables the semantics to be directly animated using a Prolog interpreter. Using this approach allows the exploration of sometimes-subtle behaviours of parallel programs and the possibility of rapid changes or additions to the semantics of the language covered that could be missed otherwise. In addition, it provides an extra check on the validity of the operational semantics.