Real-time logics: complexity and expressiveness
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Symbolic model checking for real-time systems
Information and Computation
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Is Your Model Checker on Time? On the Complexity of Model Checking for Timed Modal Logics
MFCS '99 Proceedings of the 24th International Symposium on Mathematical Foundations of Computer Science
Formal Design and Analysis of a Gear Controller
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
UPPAAL - Now, Next, and Future
MOVEP '00 Proceedings of the 4th Summer School on Modeling and Verification of Parallel Processes
A Timed Semantics for the STATEMATE Implementation of Statecharts
FME '97 Proceedings of the 4th International Symposium of Formal Methods Europe on Industrial Applications and Strengthened Foundations of Formal Methods
Model-Checking for Real-Time Systems
FCT '95 Proceedings of the 10th International Symposium on Fundamentals of Computation Theory
Formal Verification of a TDMA Protocol Start-Up Mechanism
PRFTS '97 Proceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems
Formal modeling and analysis of an audio/video protocol: an industrial case study using UPPAAL
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Formalising UML state machines for model checking
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
Flattening statecharts without explosions
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Live and let die: LSC based verification of UML models
Science of Computer Programming - Formal methods for components and objects pragmatic aspects and applications
Reasoning about real-time statecharts in the presence of semantic variations
Proceedings of the 20th IEEE/ACM international Conference on Automated software engineering
A Formal and Tool-Equipped Approach for the Integration of State Diagrams and Formal Datatypes
IEEE Transactions on Software Engineering
Design and verification of long-running transactions in a timed framework
Science of Computer Programming
On Succinctness of Hierarchical State Diagrams in Absence of Message Passing
Electronic Notes in Theoretical Computer Science (ENTCS)
Improving Software Quality in Safety-Critical Applications by Model-Driven Verification
Electronic Notes in Theoretical Computer Science (ENTCS)
Formal verification of use case maps with real time extensions
SDL'07 Proceedings of the 13th international SDL Forum conference on Design for dependable systems
Definition and implementation of a semantic mapping for UML-RT using a timed pi-calculus
Proceedings of the Second International Workshop on Behaviour Modelling: Foundation and Applications
Developing UPPAAL over 15 years
Software—Practice & Experience
Model-driven development with Mechatronic UML
Graph transformations and model-driven engineering
An automatic mapping from statecharts to verilog
ICTAC'04 Proceedings of the First international conference on Theoretical Aspects of Computing
Checking component-based embedded software designs for scenario-based timing specifications
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Model-driven development of reconfigurable mechatronic systems with MECHATRNOIC UML
MDAFA'03 Proceedings of the 2003 European conference on Model Driven Architecture: foundations and Applications
Model checking for timed statecharts
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Model-Driven architecture for hard real-time systems: from platform independent models to code
ECMDA-FA'05 Proceedings of the First European conference on Model Driven Architecture: foundations and Applications
Modeling and validation of a software architecture for the ariane-5 launcher
FMOODS'06 Proceedings of the 8th IFIP WG 6.1 international conference on Formal Methods for Open Object-Based Distributed Systems
Formalizing a domain specific language using SOS: an industrial case study
SLE'11 Proceedings of the 4th international conference on Software Language Engineering
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We present a framework for formal verification of a real-time extension of UML statecharts. For clarity, we restrict ourselves to a reasonable subset of the rich UML statechart model and extend this with real-time constructs (clocks, timed guards, and invariants). We equip the obtained formalism, called hierarchical timed automata (HTA), with an operational semantics. We outline a translation of one HTA to a network of flat timed automata, that can serve as input to the real-time model checking tool UPPAAL. This translation can be used to faithfully verify deadlock-freedom, safety, and unbounded response properties of the HTA model. We report on an XML-based implementation of this translation, use the well-known pacemaker example to illustrate our technique, and report run-time data for the formal verification part.