Formal verification of use case maps with real time extensions

Authors:
Jameleddine Hassine;Juergen Rilling;Rachida Dssouli
Affiliations:
Department of Computer Science, Concordia University, Montreal, Canada;Department of Computer Science, Concordia University, Montreal, Canada;Concordia Institute for Information Systems Engineering, Montreal, Canada
Venue:
SDL'07 Proceedings of the 13th international SDL Forum conference on Design for dependable systems
Year:
2007

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Abstract

Scenario-driven requirement specifications are widely used to capture and represent functional requirement. More recently, the Use Case Maps language (UCM), being standardized by ITU-T as part of the User Requirements Notation (URN) has gained on popularity within the software requirements community. UCM models focus on the description of functional and behavioral requirements as well as high-level designs at the early stages of system development processes. However, timing issues are often overlooked during the initial system design and treated as non-related behavioral issues and described therefore in separate models. We believe that timing aspects must be integrated into the system model during early development stages. In this paper, we present a novel approach to describe timing constraints in UCM specifications. We describe a formal operational semantics of Timed UCM in terms of Timed Automata (TA) that can be analyzed and verified with the UPPAAL model checker tool. Our approach is illustrated using a case study of the IP Multicast Routing Protocol.