Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Statecharts: A visual formalism for complex systems
Science of Computer Programming
Software Engineering Journal
A graphical representation of interval logic
International Conference on Concurrency on Concurrency 88
STATEMATE: A Working Environment for the Development of Complex Reactive Systems
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Formal verification of safety-critical systems
Software—Practice & Experience
TRIO: A logic language for executable specifications of real-time systems
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Timing assumptions and verification of finite-state concurrent systems
Proceedings of the international workshop on Automatic verification methods for finite state systems
Automata for modeling real-time systems
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The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
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Symbolic model checking for real-time systems
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A graphical interval logic for specifying concurrent systems
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Validating real-time systems by history-checking TRIO specifications
ACM Transactions on Software Engineering and Methodology (TOSEM)
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Modechart: A Specification Language for Real-Time Systems
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Logical reasoning with diagrams
Consistent composition and refinement for dependable systems
MDS '95 Proceedings of the second international conference on Mathematics of dependable systems II
Specifying and Verifying Requirements of Real-Time Systems
IEEE Transactions on Software Engineering
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Automatic Symbolic Verification of Embedded Systems
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Temporal Verification Diagrams
TACS '94 Proceedings of the International Conference on Theoretical Aspects of Computer Software
Verification with Real-Time COSPAN
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
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Real-time programming and asynchronous message passing
PODC '83 Proceedings of the second annual ACM symposium on Principles of distributed computing
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Formal specification: a roadmap
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Temporal logics for real-time system specification
ACM Computing Surveys (CSUR)
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Verification of a Radio-Based Signaling System Using the STATEMATE Verification Environment
Formal Methods in System Design
Mexitl: Multimedia in Executable Interval Temporal Logic
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Knowledge-Based Software Architectures: Acquisition, Specification, and Verification
IEEE Transactions on Knowledge and Data Engineering
Measuring Behavioral Correspondence to a Timed Concurrent Model
ICSM '01 Proceedings of the IEEE International Conference on Software Maintenance (ICSM'01)
Engineering the usability of visual formalisms: a case study in real time logics
AVI '98 Proceedings of the working conference on Advanced visual interfaces
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A Scenario-Matching Approach to the Description and Model Checking of Real-Time Properties
IEEE Transactions on Software Engineering
Towards security monitoring patterns
Proceedings of the 2007 ACM symposium on Applied computing
Expressing and organizing real-time specification patterns via temporal logics
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An evaluation of timed scenario notations
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Detecting design flaws in UML state charts for embedded software
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Formal verification of use case maps with real time extensions
SDL'07 Proceedings of the 13th international SDL Forum conference on Design for dependable systems
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REFSQ'11 Proceedings of the 17th international working conference on Requirements engineering: foundation for software quality
Verifying statemate statecharts using CSP and FDR
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Incremental specification with SCTL/MUS-T: a case study
Journal of Systems and Software
Improving model checking with context modelling
Advances in Software Engineering
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Concurrent real-time systems are among the most difficult systems to design because of the many possible interleavings of events and because of the timing requirements that must be satisfied. We have developed a graphical environment based on Real-Time Graphical Interval Logic (RTGIL) for specifying and reasoning about the designs of concurrent real-time systems. Specifications in the logic have an intuitive graphical representation that resembles the timing diagrams drawn by software and hardware engineers, with real-time constraints that bound the durations of intervals. The syntax-directed editor of the RTGIL environment enables the user to compose and edit graphical formulas on a workstation display; the automated theorem prover mechanically checks the validity of proofs in the logic; and the database and proof manager tracks proof dependencies and allows formulas to be stored and retrieved. This article describes the logic, methodology, and tools that comprise the prototype RTGIL environment and illustrates the use of the environment with an example application.