Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Statecharts: A visual formalism for complex systems
Science of Computer Programming
Comparing different approaches for specifying and verifying real-time systems
RTOSS '93 Proceedings of the tenth IEEE workshop on Real-time operating systems and software
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modechart: A Specification Language for Real-Time Systems
IEEE Transactions on Software Engineering
The STATEMATE semantics of statecharts
ACM Transactions on Software Engineering and Methodology (TOSEM)
A graphical environment for the design of concurrent real-time systems
ACM Transactions on Software Engineering and Methodology (TOSEM)
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Constraint diagrams: visualizing invariants in object-oriented models
Proceedings of the 12th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
The Unified Modeling Language user guide
The Unified Modeling Language user guide
On Communicating Finite-State Machines
Journal of the ACM (JACM)
Temporal logics for real-time system specification
ACM Computing Surveys (CSUR)
Model checking of hierarchical state machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
Symbolic Model Checking
Model Checking Large Software Specifications
IEEE Transactions on Software Engineering
Model Checking - Timed UML State Machines and Collaborations
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Towards a Formal Operational Semantics of UML Statechart Diagrams
Proceedings of the IFIP TC6/WG6.1 Third International Conference on Formal Methods for Open Object-Based Distributed Systems (FMOODS)
A UML Profile for Real-Time Constraints with the OCL
UML '02 Proceedings of the 5th International Conference on The Unified Modeling Language
The STATEMATE Verification Environment - Making It Real
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Model Checking UML Statechart Diagrams Using JACK
HASE '99 The 4th IEEE International Symposium on High-Assurance Systems Engineering
vUML: A Tool for Verifying UML Models
ASE '99 Proceedings of the 14th IEEE international conference on Automated software engineering
Implementing Statecharts in PROMELA/SPIN
WIFT '98 Proceedings of the Second IEEE Workshop on Industrial Strength Formal Specification Techniques
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
Flattening statecharts without explosions
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
An Eclipse Plug-in for Model Checking
IWPC '04 Proceedings of the 12th IEEE International Workshop on Program Comprehension
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
UML Automatic Verification Tool with Formal Methods
Electronic Notes in Theoretical Computer Science (ENTCS)
Rewrite rules and operational semantics for model checking UML statecharts
UML'00 Proceedings of the 3rd international conference on The unified modeling language: advancing the standard
Software verification with BLAST
SPIN'03 Proceedings of the 10th international conference on Model checking software
Formalising UML state machines for model checking
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
Wolf: bug hunter for concurrent software using formal methods
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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Embedded systems are used in various critical devices and correct functioning of these devices is crucial. For non-trivial devices, exhaustive testing is costly, time consuming and probably impossible. A complementary approach is to perform static model checking to verify certain design correctness properties. Though static model checking techniques are widely used for hardware circuit verification, the goal of model checking software systems remains elusive. However embedded systems fall in the category of concurrent reactive systems and can be expressed through communicating state machines. Behavior of concurrent reactive systems is more similar to hardware than general software. So far, this similarity has not been exploited sufficiently. IBM® Rational® Rose® RealTime (RoseRT) is widely used for designing concurrent reactive systems and supports UML State Charts. IBM RuleBase is an effective tool for hardware model checking. In this paper, we describe our experiments of using RuleBase for static model checking RoseRT models. Our tool automatically converts RoseRT models to the input for RuleBase, allows user to specify constraints graphically using a variation of sequence diagrams, and presents model checking results (counterexamples) as sequence diagrams consisting of states and events in the original UML model. The model checking step is seamlessly integrated with RoseRT. Prior knowledge of model checking or formal methods is not expected, and familiarity of UML sequence diagram is exploited to make temporal constraint specification and counterexample presentation more accessible. This approach brings the benefits of model checking to embedded system developers with little cost of learning.