Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Timing Analysis for Fixed-Priority Scheduling of Hard Real-Time Systems
IEEE Transactions on Software Engineering
Quantitative Temporal Reasoning
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
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Task synchronization in real-time systems
Task synchronization in real-time systems
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ACM Transactions on Software Engineering and Methodology (TOSEM)
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Proceedings of the 20th international conference on Software engineering
Automatic verification of real-time designs
Proceedings of the 21st international conference on Software engineering
Verification of real-time designs: combining scheduling theory with automatic formal verification
ESEC/FSE-7 Proceedings of the 7th European software engineering conference held jointly with the 7th ACM SIGSOFT international symposium on Foundations of software engineering
Formal verification and analysis of multimedia systems
MULTIMEDIA '99 Proceedings of the seventh ACM international conference on Multimedia (Part 1)
Refining Model Checking by Abstract Interpretation
Automated Software Engineering
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Automated Software Engineering
Compositional Reasoning in Model Checking
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
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EDTC '97 Proceedings of the 1997 European conference on Design and Test
Duration Properties over Real Time System Designs
IWSSD '00 Proceedings of the 10th International Workshop on Software Specification and Design
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Documentation Driven Development for Complex Real-Time Systems
IEEE Transactions on Software Engineering
Symbolic model checking in practice
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Embedded Systems Design
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Symbolic model checking is a technique for verifying finite-state concurrent systems. Models with up to 1030 states can often be verified in minutes. In this paper, we present a new tool to analyze real-time systems, based on this technique. We have designed a language, called Verus, for the description of real-time systems. Such a description is compiled into a state-transition graph and represented symbolically using binary decision diagrams. We have developed new algorithms for exploring the state space and computing quantitative information about the system. In addition to determining the exact bounds on the length of the time interval between two specified events, we compute the number of occurrences of an event in such an interval. This technique allows us to determine performance measures such as schedulability, response time, and system load. Our algorithms produce more detailed information than traditional methods. This information leads to a better understanding of the behavior of the system, in addition to verifying if its timing requirements are satisfied. We integrate these ideas into the Verus tool, currently under development. To demonstrate how our technique works, we have verified a robotics control system. The results obtained demonstrate that our method can be successfully applied in the analysis of real-time system designs.