Symbolic model checking in practice

  • Authors:
  • Sérgio Vale Aguiar Campos

  • Affiliations:
  • Depto. de Ciência da Computação, Universidade Federal de Minas Gerais

  • Venue:
  • SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
  • Year:
  • 1999

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Abstract

Symbolic model checking is a technique for verifying finite state reactive systems that has been very successful in practice. In this method a system being verified is represented by a state transition graph. Efficient search algorithms are used to determine if the model satisfies properties expressed as temporal logic formulas. The internal representation of the model checker uses binary decision diagrams - BDD, an extremely compact representatior of boolean formulas. Because of the BDD representation it is possible to verify extremely large and complex systems, such as aircraft control1ers, robotic controllers, the PCI local bus and the futurebus+ protocols. This work presents the method and discusses how it can be applied in practice.